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UTC 7106
ABSOLUTE MAXIMUM RATINGS(Ta=25)
PARAMETER
Supply Voltage (V+ ~ V-) Analog Input Voltage (Either Input) (Note 1) Reference Input Voltage (Either Input) Operating Temperature Range
CMOS IC
SYMBOL
VDD VI,ANG VI,REF TOP
RATINGS
15 V+ ~ VV+ ~ V0 ~ +70
UNIT
V V V
THERMAL INFORMATION
PARAMETER
Thermal Resistance (Tyical, Note 2) 50 (C/W) 75 Maximum Junction Temperature TJ 150 C Maximum Storage Temperature Range TSTG -65 ~ +150 C Maximum Lead Temperature (Soldering 10s) (QFP-44 only) TLOAD 300 C Note 1: Input voltages may exceed the supply voltages provided the input current is limited to 100A. Note 2: JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA DIP-40 QFP-44
SYMBOL
RATINGS
UNIT
ELECTRICAL CHARACTERISTICS (Note 3)
PARAMETER SYSTEM PERFORMANCE
Zero Input Reading Ratiometric Reading
SYMBOL
RZ RR
TEST CONDITIONS
VIN=0.0V, Full Scale=200mV VIN=VREF, VREF=100mV -VIN=+VIN200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Full Scale=200mV or Full Scale=2V Maximum Deviation from Best Straight Line Fit (Note 5) VCM=1V,VIN=0V, Full Scale=200mV(Note 5) VIN=0V,Full Scale=200mV (Peak-To-Peak Value Not Exceeded 95% of Time) VIN=0(Note 5) VIN=0, 0 ~ 70 (Note 5) VIN=199mV, 0 ~ 70, (Ext.Ref.0ppm/) (Note 5) VIN=0 25k Between Common and Positive Supply (With Respect to +Supply)
MIN
-000.0 999
TYP
000.0 999/1000
MAX
+000.0 1000
UNIT
Digital Reading Digital Reading Counts
Rollover Error
ER
0.2
1
Linearity
L
0.2
1
Counts
Common Mode Rejection Ratio Noise Leakage Current Input Zero Reading Drift Scale Factor Temperature Coefficient End Power Supply Character V+ Supply Current COMMON Pin Analog Common Voltage
CMRR VN IL DZR T,S IEP VCOM
50 15 1 0.2 1 1.0 2.4 3.0 10 1 5 1.8 3.2
V/V V pA V/ ppm/ mA V
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UTC 7106
PARAMETER
Temperature Coefficient of Analog Common
CMOS IC
SYMBOL
T,A
TEST CONDITIONS
25k Between Common and Positive Supply (With Respect to +Supply)
MIN
TYP
80
MAX
UNIT
ppm/
DISPLAY DRIVER Peak-To-Peak Segment Drive VD,PP V+ ~ V-=9V(Note 4) 4 5.5 6 V Voltage Peak-To-Peak Backplane Drive Voltage Note 3: Unless otherwise noted, specifications apply to the UTC 7106 at Ta=25, fCLOCK=48kHz, UTC 7106 is tested in the circuit of Figure 1. Note 4: Back plane drive is in phase with segment drive for"off"segment,180 degrees out of phase for"on" segment .Frequency is 20 times conversion rate. Average DC component is less than 50mV. Note 5: Not tested, guaranteed by design.
TYPICAL APPLICATIONS AND TEST CIRCUITS (LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE)
+
IN R1 R4 REF HI 36 REF LO 35 R5 C1 CREF + 34 CREF - 33 COM 32 C5
+
9V
DISPLAY BP 21 G2 25 C3 24 A3 23 G3 22
R3 OSC 1 40 OSC 2 39 OSC 3 38
C4 TEST 37
C2 R2 C3 A-Z 29 BUFF 28 INT 27 V- 26
IN HI 31
IN LO 30
UTC 7106
20 POL 19 AB4
DISPLAY
C1=0.1F C2=0.47F C3=0.22F C4=100pF C5=0.02F R1=24k R2=47k R3=91k R4=1k R5=1M
7 G1
9 D2
10 C2
15 D3
5 A1
11 B2
12 A2
14 E2
16 B3
DESIGN INFORMATION SUMMARY SHEET
*OSCILLATOR FREQUENCY fosc=0.45/RC COSC>50pF, ROSC>50k fOSC (Typ)=48kHz *OSCILLATOR PERIOD tOSC=RC/0.45 *INTEGRATION CLOCK FREQUENCY
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18 E3
F1
13 F2
17 F3
2 D1
3 C1
4 B1
8 E1
1 V+
6
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fCLOCK=fOSC/4 *INTEGRATION PERIOD tINT=1000x(4/fOSC) *60/50Hz REJECTION CRITERION tINT/t60Hz or tINT/t50Hz=Integer *OPTIMUM INTEGRATION CURRENT IINT=4A *FULL SCALE ANALOG INPUT VOLTAGE VINFS (Typ)=200mV or 2V *INTEGRATE ESISTOR RINT= VINFS/ IINT
*INTEGRATE
CMOS IC
CAPACITOR CINT=(tINT)(IINT)/ VINT
*INTEGRATOR OUTPUT VOLTAGE SWING VINT=(tINT)(IINT)/ CINT *VINT MAXIMUM SWING (V- + 0.5V)*POWER SUPPLY: SINGLE 9V V+ - V- =9V
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VGNDV+ - 4.5V Digital supply is generated by internal parts. *DISPLAY: LCD Type: Direct drive with digital logic supply amplitude.
CMOS IC
TYPICAL INTEGRATOR AMPLIFIER OUTPUT WAVEFORM (INT PIN)
AUTO ZERO PHASE SIGNAL INTEGRATE (COUNTS) PHASE FIXED 2999-1000 1000 COUNTS
DE-INTEGRATE PHASE 0 - 1999 COUNTS
TOTAL CONVERSION TIME=4000 x tCLOCK=16,000 x tosc
DETAILED DESCRIPTION
ANALOG SECTION
Figure 1 shows the Analog Section for the UTC 7106. Each measurement cycle is divided into three phases. They are(1) auto-zero(A-Z), (2)signal integrate (INT)and (3)de-integrate(DE).
AUTO-ZERO PHASE
During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case. the offset referred to the input is less than 10V.
SIGNAL INTEGRATE PHASE
During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. if, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined.
DE-INTEGRATE PHASE
The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: DISPLAY COUNT=1000( VIN/ VREF ).
DIFFERENTIAL INPUT
The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst
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CMOS IC
case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity.
DIFFERENTIAL REFERENCE
The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection)
STRAY CREF + V+ 34 REF HI
CREF REF LO 35 A-Z
STRAY CREF 33
RINT BUFFER V+ 28 1 29
CAZ A-Z
INTEGRATOR
CINT INT 27 TO DIGITAL SECTION
36 A-Z
10A 31 IN HI INT A-Z N COMMON 32 INT IN LO 30 VDE+ DEA-Z AND DE() DEDE+
+
2.8V
+
+
INPUT HIGH
A-Z
6.2V
+
COMPARATOR
INPUT LOW
FIGURE 1. ANALOG SECTION
ANALOG COMMON
This pin is included primarily to set the common mode voltage for battery operation (UTC 7106) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate(>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (15), and a temperature coefficient typically less than 80ppm/. The UTC 7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 1. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage(power supply common for instance).In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the IC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is
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V+ V REF HI REF LO 6.8V ZENER Iz V
CMOS IC
V+
only 10A of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference.
6.8k
UTC 7106
REF HI REF LO
20k ICL8069 1.2V REFERENCE
UTC 7106
VFIGURE 2A.
COMMON
FIGURE 2B. FIGURE 2. USING AN EXTERNAL REFERENCE
TEST
The TEST pin serves two function. On the UTC 7106 it is coupled to the internally generated digital supply through a 500 resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 3 and 4 show such an application. No more than a 1mA load should be applied. The second function is a "lamp test". When TEST is pulled high (to V+) all segments will be turned on and the display should read "1888". The TEST pin will sink about 15mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave) . This may burn the LCD display if maintained for extended periods.
V+ 1M TO LCE DECIMAL POINT 21 37 TO LCD BACKPLANE
V+ BP UTC 7106
V+
UTC 7106 BP TEST
DECIMAL POINT SELECT
TO LCD DECIMAL POINTS
TEST
CD4030
GND FIGURE 3. SIMPLE INVERTER FOR FIXED DECIMAL POINT FIGURE 4. EXCLUSIVE "OR" GATE FOR DECIMAL POINT DRIVE
DIGITAL SECTION
Figure 5 show the digital section for the UTC 7106, respectively. In the UTC 7106, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane(BP) voltage is switchied. The BP frequency is the clock frequency divided by 800. For three readings/sec, this is a 60Hz square wave with a nominal amplitude of 5V. The
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CMOS IC
segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments.
a a f g b e d c e b f
a b g c d e f
a b g c d 21 BACKPLANE
LCD PHASE DRIVER TYPICAL SEGMENT OUTPUT V+ 0.5mA SEGMENT OUTPUT 2mA INTERNAL DIGITAL GROUND 7 SEGMENT DECODE 7 SEGMENT DECODE 7 SEGMENT DECODE
/200
LATCH
100 s 1000 s COUNTER COUNTER TO SWITCH DRIVERS FROM COMPARATOR OUTPUT
,
,
10 s COUNTER
,
1s COUNTER
,
1 CLOCK LOGIC CONTROL 6.2V 500 INTERNAL DIGITAL GROUND VTH=1V 37
V+
*
/4
TEST
*
THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY 40 OSC 1 OSC 2 39 OSC 3 38 26
V-
FIGURE 5. DIGITAL SECTION
SYSTEM TIMING
Figure 6 shows the clocking arrangement used in the UTC 7106. Two basic clocking arrangements can be used: 1. Figure 6A. An external oscillator connected to pin 40. 2. Figure 6B. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate(0 to 2000 counts) and auto-zero(1000 ~ 3000 counts). For signals less than full scale. auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 33 1/3kHz, etc should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz, 40kHz, etc would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).
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INTERNAL TO PART INTERNAL TO PART
CMOS IC
/4
CLOCK
/4
CLOCK
40
39
38
40
39 R
38 C RC OSCILLATOR
TEST FIGURE 6A FIGURE 6B
FIGURE 6. CLOCK CIRCUITS
COMPONENT VALUE SELECTION Integrating Resistor
Both the buffer amplifier and the integrator have a class A output stage with 100A of quiescent current. They can supply 4A of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470k is near optimum and similarly a 47k for a 200mV scale.
Integrating Capacitor
The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing(approximately. 0.3V from either supply).In the UTC 7106, when the analog COMMON is used as a reference, a nominal+2V fullscale integrator swing is fine. For three readings/second (48kHz clock) nominal values for CINT are 0.22F and 0.10F, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorptiont to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost.
Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47F capacitor is recommended. On the 2V scale, a 0.047F capacitor increases the speed of recovery from overload and is adequate for noise on this scale.
Reference Capacitor
A 0.1F capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e.,the REF LO pin is not at analog COMMON)and a 200mV scale is used, a larger value is required to prevent roll-ovre error. Generally 1F will hold the roll-over error to 0.5 count in this instance.
Oscillator Components
For all ranges of frequency a 91k resistor is recommended and the capacitor is selected from the equation: f= 0.45/RC For 48kHz Clock (3 Readings/sec), C=100pF.
Reference Voltage
The analog input required to generate full scale output (2000 counts) is: VIN=2VREF.Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively.However,in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the
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TYPICAL APPICATIONS
CMOS IC
transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF=0.341V. Suitable values for integrating resistor and capacitor would be 120k and 0.22F. This makes the system slightly quieter and also avoids a divider network on the input.
The UTC 7106 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters.
TO PIN 1 OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF CREF COMMON IN HI IN LO A-Z BUFF INT VG2 C3 A3 G3 BP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TO BACKPLANE TO DISPLAY 0. 22F 0. 47F 47k 1k 0.1F 1M 0. 01F + 9V + IN 22k 100pF 91k SET VREF =100mV
Values shown are for 200mV full scale,3 readings/sec.,floating supply voltage(9V battery).
FIGURE 7. USING THE INTERNAL REFERENCE
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TYPICAL APPLICATIONS (Continued)
CMOS IC
OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF CREF COMMON IN HI IN LO A-Z BUFF INT VG2 C3 A3 G3 BP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
TO PIN 1 91k SET VREF =100mV
100pF
25k 24k 0.1F 1M 0. 01F 0. 047F 470k 0. 22F +
V+
IN
V-
TO DISPLAY
FIGURE 8. RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE
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TYPICAL APPLICATIONS (Continued)
CMOS IC
TO PIN 1 OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF CREF COMMON IN HI IN LO A-Z BUFF INT VG2 C3 A3 G3 BP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TO BACKPLANE TO DISPLAY 0. 22F 0.01F 0. 47F 47k 9V 0.1F 100pF 91k SCALE FACTOR ADJUST 22k 100k 1M 100k 220k ZERO ADJUST
SILICON NPN MPS 3704 OR SIMILAR
A sillicon diode-connected transistor has a temperature coefficient of about -2mV/ . Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading.The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading
FIGURE 9. USED AS A DIGITAL CENTIGRADE THERMOMETER
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TYPICAL APPLICATIONS (Continued)
CMOS IC
V+ 1 2 TO LOGIC VDD 3 4 5 6 7 8 9 V+ D1 C1 B1 A1 F1 G1 E1 D2 OSC1 40 OSC2 39 OSC3 38 TEST REF LO 37 35 TO LOGIC GND REF HI 36 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 BP 21 V-
10 C2 11 B2 12 A2 13 F2 14 E2 15 D3 16 B3 O/RANGE 17 F3 18 E3 19 AB4 20 POL U/RANGE
CD4077
FIGURE 10. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM UTC 7106 OUTPUTS
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TYPICAL APPLICATIONS (Continued)
CMOS IC
TO PIN 1 OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF CREF COMMON IN HI IN LO A-Z BUFF INT VG2 C3 A3 G3 BP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TO BACKPLANE TO DISPLAY 0.22F 0.47F 47k + 10F 9V 100pF (FOR OPTIMUM BANDWIDTH) 1k 0.1F 22k 470k 2.2M 1F 10k 4.3k 10k 1F 1F 0.22F 1N914 100pF 91k 10F SCALE FACTOR ADJUST (VREF=100mV FOR AC TO RMS) CA3140 5F 100k
+ -
AC IN
Test is used as a common-mode reference level to ensure compatiblity with most op amps.
FIGURE 11. AC TO DC CONVERTER WITH UTC 7106
UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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